Principal Engineer - Design (ASIC)

Company: FHLB Des Moines
Location: San Jose
Posted on: October 16, 2024

Job Description:

Principal Engineer - Design (ASIC) page is loaded Principal Engineer - Design (ASIC) Apply locations CA - San Jose - 3870 N. First St CA - Roseville time type Full time posted on Posted 30+ Days Ago job requisition id R2133-24 Are you looking for a unique opportunity to be a part of something great? Want to join a 20,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology, Inc.People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip's nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values ; we affectionately refer to it as the Aggregate System and it's won us countless awards for diversity and workplace excellence.Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.Visit our careers page to see what exciting opportunities and company perks await!Job Description: The successful -candidate will join the rapidly growing Data Center Solutions (DCS) business unit at Microchip. DCS has a broad portfolio of products widely deployed by the industry's cutting-edge server/storage OEMs and hyperscale datacenters. Customers deploy DCS solutions into applications ranging from Big Data capacity storage to artificial intelligence and machine learning that are helping to shape the next digital age. Our product portfolio includes SAS/PCIe/NVMe/CXL products that connect, manage, and secure the world's information, including Flash Controllers, High Performance Switches, RAID Controllers and Memory Controllers. Join a team where you can expand your skill set and drive key elements of the industry's technology leadership. As a Principal Engineer - Design (ASIC) in the Microchip Data Center Solutions group, you will get hands-on experience developing our next generation of SSD Flash controller SOC products. This will involve taking a design from initial concept to production form. Throughout you will work beside experienced engineers and be exposed to Microchip's Best-In-Class engineering practices. Working side-by-side with some of the brightest minds and most innovative people in the industry, you won't just fill a position, you will be given an opportunity to work on a team where your contributions matter. You will be challenged and encouraged to discover the power of innovation. Microchip fosters continuous learning in a challenging and rewarding environment. If this sounds like the kind of environment you'd like to participate in, we'd like to hear from you! Responsibilities include:

• Perform RTL design of IP and SoC sub-systems, as well as integration into SoCs, by working with cross-functional teams globally
• Pre-silicon verification support and debug
• Emulation and debug of the IP and solution
• Post-silicon integration, bring-up, and validation
• Learning and dynamically applying knowledge of the SoC, protocols and standards
• Effectively presenting technical information to small teams of engineers
• The role and responsibilities will grow with the individual candidate's skills and interests
• Ownership of complex digital integrated circuits at the block, subsystem or device level, which are coded in Verilog, System Verilog
• Translate complex architectural requirements into microarchitecture that is realizable in targeted technology node
• Lead and mentor fellow design engineers; scope and schedule deliverables
• Define subsystem/block feature sets, describe design and implementation details into engineering documents and registers documents
• Communicate regularly with the design and verification team in multiple locations to resolve issues, communicate status and solve technical problems
• Communicate with architects to justify design implementation decisions and associated trade-offs
• Support emulation, ASIC lab validation including lab debug and providing logic modifications and workarounds
• Become versed in applicable storage and computer interface protocol standards Requirements/Qualifications:
  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering or equivalent
  • 10+ years related experience
  • PCIE knowledge and experience
  • RTL Design - Experience in RTL Design using System Verilog
  • Experience and understanding of complex ASIC design flows, including block and chip level simulation and debug, logic synthesis, static timing analysis, layout and revision control
  • Scripting and programming skills using csh, bash, perl, python, tcl, etc
  • Excellent analytical and debugging skills and the ability to proactively solve issues.
  • Working knowledge of DFT
  • Excellent communication (written and verbal), and documentation skills
  • Excellent teamwork and time management skills, self-direction, the ability to work under pressure and the desire to excel in a competitive environment Travel Time:0% - 25%Physical Attributes:Feeling, Handling, Hearing, Seeing, Talking, Works Alone, Works Around OthersPhysical Requirements:80% sitting, 10% walking, 10% standing; 100% in doors; Usual business hoursPay Range:We offer a total compensation package that ranks among the best in the industry. It consists of competitive base pay, restricted stock units, and quarterly bonus payments. In addition to these components, our package includes health benefits that begin day one, retirement savings plans, and an industry leading ESPP program with a 2 year look back feature. Find more information about all our benefits at the link below:Benefits of working at Microchip The annual base salary range for this position, which could be performed in California, is $75,000 - $232,000.* *Range is dependent on numerous factors including job location, skills and experience. Microchip Technology Inc is an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law.
    
    For more information on applicable equal employment regulations, please refer to the EEO is the Law Poster and the EEO is the Law Poster Supplement . Please also refer to the Pay Transparency Policy Statement . At Microchip, employees are our greatest strength. As one of the top performing semiconductor companies in the world, we are led by a set of guiding values and a mission to become the very best embedded control solutions company ever. We work tirelessly to create a company culture that highlights how important every employee is to our mission.
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Keywords: FHLB Des Moines, Tracy , Principal Engineer - Design (ASIC), Engineering , San Jose, California